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Burst EDO, while a good idea, was dead before it ever was born. The addition of a burst
mode, along with a dual bank architecture would have provided the 4-1-1-1 access times
at 66MHz that many expected with SDRAM. Burst mode is an advancement over page
mode, in that after the first address input, the next 3 addresses are generated internally,
thereby eliminating the time necessary to input a new column address. Unfortunately,
Intel decided that EDO was no longer viable, and SDRAM was their preferred memory
architecture so they did not implement support of BEDO into their chipsets. In fact,
several large memory manufacturers had put considerable time and money into the
development of SDRAM over the past decade, and were not very happy with the BEDO
design.
Except for support of bus speeds of 100MHz and faster, BEDO would probably have
been a much faster and more stable memory than SDRAM. Essentially, BEDO lost
support as much for political and economic reasons as for technical ones, it seems.
Synchronous Operation
Once it became apparent that bus speeds would need to run faster than 66MHz, DRAM
designers needed to find a way to overcome the significant latency issues that still
existed. By implementing a synchronous interface, they were able to do this and gain
some additional advantages as well.
With an asynchronous interface, the processor must wait idly for the DRAM to complete
its internal operations, which typically takes about 60ns. With synchronous control, the
DRAM latches information from the processor under control of the system clock. These
latches store the addresses, data and control signals, which allows the processor to handle
other tasks. After a specific number of clock cycles the data becomes available and the
processor can read it from the output lines.
Another advantage of a synchronous interface is that the system clock is the only timing
edge that needs to be provided to the DRAM. This eliminates the need for multiple
timing strobes to be propagated. The inputs are simplified as well, since the control
signals, addresses and data can all be latched in without the processor monitoring setup
and hold timings. Similar benefits are realized for output operations as well.
JEDEC SDRAM
All DRAMs that have a synchronous interface are known generically as SDRAM. This
includes CDRAM (Cache DRAM), RDRAM (Rambus DRAM), ESDRAM (Enhanced
SDRAM) and others, however the type that most often is called SDRAM is the JEDEC
standard synchronous DRAM.
JEDEC SDRAM not only has a synchronous interface controlled by the system clock, it
also includes a dual-bank architecture and burst mode (1-bit, 2-bit, 4-bit, 8-bit and full
page). A `mode register' that can be set at power-on and changed during operation
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