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memory, the goal of a cache DRAM is to hold the most frequently used data in the
SRAM cache to minimize accesses to the slower DRAM. One advantage to the on-chip
SRAM is that a wider bus can be used between the SRAM and DRAM, effectively
increasing the bandwidth and increasing the speed of the DRAM even when there is a
cache miss.
As with DDR SDRAM, there is currently at least one Socket 7 chipset with support for
ESDRAM. The deciding factor in determining which of these solutions will succeed will
likely be the initial cost of the modules. Current estimates show the cost of ESDRAM at
about 4 times that of existing DRAM solutions, which will likely not go over well with
most users.
Protocol Based DRAM
All of the previously discussed DRAM have separate address, data and control lines
which limits the speed at which the device can operate with current technology. In order
to overcome this limitation, several designs implement all of these signals on the same
bus. The two protocol based designs currently getting the most attention are SyncLink
DRAM (now called SLDRAM due to trademark issues) and Direct Rambus DRAM
(DRDRAM) licensed by Rambus, Inc.
DRDRAM
Intel has placed their money on the proprietary memory design developed by Rambus,
Inc. On the surface, this looks to be a very fast solution for system memory due to its fast
operation (up to 800MHz). The reality is, however, that the design is only up to twice as
fast as current SDRAM operation due to the smaller bus width (16 bits vs. 64 bits).
Despite the claims from Intel and Rambus, Inc., there are some potentially serious issues
which need to be addressed with this technology. The higher speeds require short wire
lengths and additional shielding to prevent problems with EMI. In addition, latency times
are actually worse than currently available fast SDRAM. Since most of today's
applications do not actually utilize the full bandwidth of the memory bus even today,
simply increasing the bandwidth while ignoring latency issues will likely not provide any
real performance improvements. In addition, processors operating with 800MHz bus
speeds will certainly require more than double the current memory bandwidth.
While these issues are serious enough, the biggest drawback to the technology is that it is
proprietary technology. Manufacturers wishing to implement a solution with DRDRAM
will be required to pay a royalty to Intel and Rambus, Inc., and will also have no real
control over the technology. This is not an attractive outlook for most memory
manufacturers who have no desire to essentially become chip foundries.
SLDRAM
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