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above 83MHz. In order to bring some semblance of order to the marketplace, Intel
introduced the PC100 specification as a guideline to manufacturers for building modules
that would function properly on their upcoming i440BX. With the PC100 specification,
Intel laid out a number of guidelines for trace lengths, trace widths and spacing, number
of PCB layers, EEPROM programming specs, etc.
There is still quite a bit of confusion regarding what a `true' PC100 module actually
consists of. Unfortunately, there are quite a few modules being sold today as PC100, yet
do not operate reliably at 100MHz. While the chip speed rating is used most often to
determine the overall performance of the chip, a number of other timings are very
important. tRCD (RAS to CAS Delay), tRP (RAS precharge time) and CAS Latency all
play a role in determining the fastest bus speed the module will operate on to still achieve
a 4-1-1-1 timing.
PC100 SDRAM on a 100MHz (or faster) system bus will provide a performance boost
for Socket 7 systems of between 10% and 15%, since the L2 cache is running at system
bus speed. Pentium II systems will not see as big a boost, because the L2 cache is running
at ½ processor speed anyway, with the exception of the cacheless Celeron chips of
course.
DDR SDRAM
One limitation of JEDEC SDRAM is that the theoretical limitation of the design is
125MHz, though technology advances may allow up to 133MHz operation. It is obvious
that bus speeds will need to increase well beyond that in order for memory bandwidth to
keep up with future processors. There are several competing new standards on the
horizon that are very promising, however most of them require special pinouts, smaller
bus widths, or other design considerations. In the short term, Double Data Rate SDRAM
looks very appealing. Essentially, this design allows the activation of output operations
on the chip to occur on both the rising and falling edge of the clock. Currently, only the
rising edge signals an event to occur, so the DDR SDRAM design can effectively double
the speed of operation up to at least 200MHz.
There is already one Socket 7 chipset that has support for DDR SDRAM, and more will
certainly follow if manufacturers decide to make this memory available. In this industry,
many times it is the first to market that gains the support, rather than the best technology.
Enhanced SDRAM (ESDRAM)
In order to overcome some of the inherent latency problems with standard DRAM
memory modules, several manufacturers have included a small amount of SRAM directly
into the chip, effectively creating an on-chip cache. One such design that is gaining some
attention is ESDRAM from Ramtron International Corporation.
ESDRAM is essentially SDRAM, plus a small amount of SRAM cache which allows for
lower latency times and burst operations up to 200MHz. Just as with external cache
|
Earn Money
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Paramount Airways
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